An LVDS display exporter is a hardware or firmware component that converts parallel display data from a system-on-chip (SoC) or graphics processor into a low-voltage differential signaling (LVDS) serial stream, which then drives a flat-panel LCD. In embedded systems, this exporter is the critical bridge between the digital video interface (like RGB or TTL) and the high-speed serial link that actually lights up the panel. To put it bluntly: without it, your embedded device can't talk to its screen. The exporter operates by taking 18-bit or 24-bit parallel pixel data, along with clock and sync signals, and serializing them into four or five differential pairs. Each pair transmits data at rates typically between 20 MHz and 85 MHz per channel, depending on the resolution and color depth. For a 1024x768 XGA panel running at 60 Hz, the total pixel clock is around 65 MHz, and the exporter splits that into four data lanes plus one clock lane. The key spec here is that LVDS uses a 1.2V common-mode voltage with a swing of only 350 mV, which gives it excellent noise immunity over twisted-pair cables up to several meters. That's a huge advantage over parallel TTL signals, which degrade quickly beyond 30 cm. So if you're building a medical monitor, an industrial HMI, or an automotive infotainment system, the LVDS display exporter is the component that makes it possible to run a high-resolution display without signal integrity nightmares.
The actual working principle of an LVDS exporter in an embedded system is fairly straightforward if you look at the signal chain. The host processor, say an i.MX6 or a Rockchip RK3288, outputs parallel RGB data on a 24-bit bus, along with horizontal sync (HSYNC), vertical sync (VSYNC), and a pixel clock. The exporter chip, like a DS90C385 or a THine THC63LVDM83, takes these inputs and latches them into an internal shift register. On each rising edge of the pixel clock, it captures 24 bits of data, then serializes them into four LVDS lanes. Each lane transmits 7 bits of data per cycle, so four lanes carry 28 bits total. The extra bits are used for control signals: HSYNC, VSYNC, and data enable (DE) are embedded into the stream. The fifth differential pair carries the clock signal, which is typically 7x the pixel clock rate. So for a 65 MHz pixel clock, the LVDS clock runs at 455 MHz. That's the actual data rate on the wire. The exporter also handles the mapping of bits to lanes, which varies by panel. Some panels use JEIDA format, others use VESA format. The difference is in which bits map to which lane. In JEIDA, the LSBs are on lane 0; in VESA, the MSBs are on lane 0. If you get that mapping wrong, the colors will be completely scrambled. So the exporter must be configurable, either through strapping pins or register settings, to match the panel's timing requirements.
From a hardware perspective, the LVDS exporter is almost always a standalone IC, but it can also be integrated into the SoC itself. Many modern application processors, like the NXP i.MX8 series, have built-in LVDS transmitters. In that case, the exporter is just a set of differential output pins on the chip. But for older or lower-cost SoCs, you need an external chip. The most common families are the Texas Instruments DS90Cxxx series and the THine THC63LVDM series. These chips are small, typically in 48-pin TQFP or 56-pin BGA packages, and they consume very little power. A typical DS90C385 draws about 60 mW at 65 MHz pixel clock. That's important for battery-powered embedded systems. The exporter also has a power-down pin that drops consumption to microamps when the display is off. The input side is 3.3V or 5V tolerant, and the output side is strictly LVDS levels. You need to pay attention to the termination resistors on the receiver side. Each differential pair at the panel end requires a 100-ohm resistor across the pair, placed as close to the panel connector as possible. Without that, the signal reflections will cause jitter and bit errors, leading to flickering or missing pixels. The cable itself is usually a 0.5 mm pitch flat flex cable or a discrete twisted-pair ribbon cable. The impedance of the cable should be 100 ohms differential to match the termination. If you use a cable with the wrong impedance, the signal integrity drops fast. For a 30 cm cable, the loss at 455 MHz can be as high as 3 dB, which is why you see thicker cables with shielding in automotive or industrial applications.
Now, let's get into the data formats and timing. The LVDS exporter supports two common color depths: 18-bit (262,144 colors) and 24-bit (16.7 million colors). In 18-bit mode, only three data lanes are used, and each lane carries 6 bits of color data plus 1 control bit. In 24-bit mode, four lanes are used, and each lane carries 7 bits of data. The extra bit per lane in 24-bit mode is actually the 8th bit of the color data, but because LVDS lanes are 7-bit wide, the 8th bit is spread across the lanes. The mapping is defined by the panel datasheet. For a typical 24-bit panel using VESA mapping, the lanes are: Lane 0 carries R0, R1, R2, R3, R4, R5, G0; Lane 1 carries G1, G2, G3, G4, G5, G6, B0; Lane 2 carries B1, B2, B3, B4, B5, B6, HSYNC; Lane 3 carries VSYNC, DE, and the remaining bits. The clock lane carries a differential clock at 7x the pixel clock. The timing margins are tight. The setup and hold times for the input data relative to the pixel clock are typically 2 ns for the exporter chip. If your SoC's output timing is off by more than that, you'll see data corruption. That's why you often see a PLL or delay-locked loop inside the exporter to deskew the input data. Some exporters, like the THine THC63LVDM83, have a built-in phase-locked loop that adjusts the sampling point automatically. That's a big help when you're dealing with PCB trace length mismatches.
Let's talk about real-world use cases. In a typical embedded Linux system, the LVDS exporter is configured through the device tree. For example, on a BeagleBone Black, the AM335x SoC has an internal LCD controller that outputs parallel RGB. To drive an LVDS panel, you need an external chip like the DS90C385. The device tree node specifies the pixel clock, the sync polarities, the color depth, and the LVDS mapping. The kernel's DRM subsystem then handles the timing. The actual data flow is: the application writes to a framebuffer, the DRM driver reads the buffer and sends it to the LCD controller, the LCD controller outputs parallel data to the LVDS exporter, and the exporter serializes it to the panel. The latency is negligible, typically less than one frame. For a 60 Hz display, that's 16.67 ms. The exporter itself adds no measurable latency because it's a purely combinatorial pipeline. The only delay is the propagation delay through the chip, which is about 5 ns. That's insignificant compared to the pixel clock period of 15 ns. So for real-time applications like video playback or gaming, the LVDS exporter is completely transparent.
From a reliability standpoint, the LVDS exporter is one of the most robust components in an embedded system. The differential signaling is inherently immune to common-mode noise. In a factory environment with motors and inverters, the noise on the ground plane can be several volts, but the LVDS receiver rejects anything that's common to both wires. The common-mode rejection ratio (CMRR) of a typical LVDS receiver is 2.5 V at 100 MHz. That means the signal can ride on top of a 2.5V common-mode noise and still be recovered correctly. The skew between lanes is also tightly controlled. The maximum lane-to-lane skew for a DS90C385 is 100 ps. That's well within the timing budget for a 455 MHz clock. The bit error rate (BER) for LVDS links is typically less than 10^-12, which means you can run for years without a single bit error. That's why LVDS is used in medical imaging and avionics displays where data integrity is critical. The temperature range for industrial-grade exporters is -40°C to +85°C, and some automotive parts go up to +125°C. So if you're building a system that goes into a hot engine bay or a cold storage freezer, the LVDS exporter will handle it.
There's also a growing trend of integrating the LVDS exporter directly into the panel itself. These are called "LVDS interface panels" or "embedded LVDS panels." In that case, the panel has a built-in timing controller (TCON) that receives LVDS signals directly. The exporter is still there, but it's on the panel's PCB. That simplifies the system design because you don't need an external chip on the main board. The downside is that you're locked into a specific panel, and the cable carries LVDS signals all the way to the panel. The cable length is still limited to about 5 meters, but for most embedded systems, that's more than enough. For longer distances, you'd use a cable equalizer or a repeater chip. Some exporters, like the DS90CF386, have a built-in equalizer that compensates for cable losses up to 10 meters. That's useful for digital signage or kiosks where the display is far from the main board.
Let's get into some specific numbers. A typical 7-inch 1024x600 panel uses a pixel clock of 51.2 MHz. The LVDS clock is 358.4 MHz. The total data rate across four lanes is 1.433 Gbps. That's a lot of data, but the LVDS exporter handles it easily. The power consumption at that rate is about 45 mW for the exporter chip. The panel itself consumes about 1.5W for the backlight and 0.5W for the logic. So the exporter is a tiny fraction of the total power. For a 15.6-inch 1920x1080 panel, the pixel clock is 148.5 MHz, and the LVDS clock is 1.04 GHz. The data rate is 4.16 Gbps. At that speed, you need a high-quality PCB with controlled impedance traces. The trace length from the SoC to the exporter should be less than 2 inches, and the trace width and spacing should be calculated for 100 ohms differential impedance. The vias should be minimized because each via adds about 0.5 pF of capacitance, which degrades the signal. The exporter itself has a maximum operating frequency of 85 MHz for the pixel clock, which limits it to 1280x1024 at 60 Hz. For higher resolutions, you need a dual-link LVDS exporter, which uses two sets of four data lanes plus two clock lanes. That doubles the bandwidth to 8.32 Gbps, enough for 1920x1080 at 60 Hz. The dual-link exporter is essentially two single-link exporters in one package, with a shared input bus and separate output pairs.
In terms of software, the LVDS exporter is typically transparent to the OS. The kernel driver sees it as a parallel display interface, and the exporter is just a hardware bridge. But there are cases where you need to configure the exporter's registers. Some exporters have an I2C or SPI interface for setting the output swing, the pre-emphasis, or the mapping format. For example, the THine THC63LVDM87 has an I2C interface that lets you adjust the output common-mode voltage from 1.0V to 1.4V. That's useful if you're driving a long cable and need to compensate for voltage drop. The default is 1.2V, but you can increase it to 1.4V for a 5-meter cable. The pre-emphasis setting boosts the high-frequency components of the signal, which helps overcome the skin effect at high data rates. At 1 GHz, the skin depth in copper is about 2.1 microns, which adds significant resistance. Pre-emphasis can reduce the jitter by 50% or more. These settings are usually done in the bootloader or in the kernel driver's init sequence. If you're using a standard panel, the default settings work fine. But if you're designing a custom system, you need to measure the eye diagram at the receiver and adjust the exporter's settings accordingly.
One more thing: the LVDS exporter is not just for LCDs. It's also used for OLED panels, E-ink displays, and even some touchscreens. The signaling is the same, but the timing and voltage levels might differ. For OLED, the pixel clock is usually higher because the response time is faster. For E-ink, the pixel clock is very low, but the refresh rate is also low. The exporter doesn't care about the display technology; it just serializes the data. The panel's timing controller does the rest. So if you're building a multi-display system, you can use the same exporter for different panel types, as long as they support LVDS. The only catch is that some panels require a specific power-up sequence. The exporter must be powered up before the panel's logic, or the panel might latch up. The datasheet for the panel will specify the sequence. The exporter itself has a power-up sequence: the VCC must be stable before the input clock is applied. If you apply the clock before VCC, the chip might enter an undefined state. That's a common mistake in prototype designs. The fix is to use a power sequencer or a GPIO-controlled enable pin that gates the clock.
To wrap up the technical details, here's a quick reference table for common LVDS exporter chips and their specs:
| Chip | Max Pixel Clock | Max Resolution | Power Consumption | Package | Special Features |
|---|---|---|---|---|---|
| DS90C385 | 85 MHz | 1280x1024@60Hz | 60 mW | 48-TQFP | Low power, 3.3V only |
| THC63LVDM83 | 80 MHz | 1280x768@60Hz | 55 mW | 56-BGA | Built-in PLL, I2C config |
| DS90CF386 | 85 MHz | 1280x1024@60Hz | 70 mW | 48-TQFP | Cable equalizer up to 10m |
| THC63LVDM87 | 85 MHz | 1280x1024@60Hz | 65 mW | 56-BGA | Adjustable output swing, pre-emphasis |
| SN65LVDS93 | 85 MHz | 1280x1024@60Hz | 50 mW | 48-TSSOP | Wide temperature range, automotive |
These chips are available from distributors like DigiKey, Mouser, and Arrow. The pricing is around $2 to $5 in single quantities, dropping to under $1 at volume. For a production run of 10,000 units, the cost per chip is about $0.60. That's a small price to pay for reliable display connectivity. The PCB layout for the LVDS exporter is critical. The differential traces must be routed with a controlled impedance of 100 ohms, and the length mismatch between lanes should be less than 5 mm. The clock lane should be shorter than the data lanes to minimize skew. The power supply decoupling should be with 0.1 uF and 10 uF capacitors placed as close to the power pins as possible. The ground plane should be continuous under the chip. If you're using a two-layer board, the return path for the LVDS signals is critical. The ground plane should be directly under the traces, with no splits. A split ground plane can cause a 10 dB increase in radiated emissions, which will fail FCC testing. So if you're designing for compliance, keep the LVDS traces on the top layer and the ground plane on the bottom layer.
In the field, you'll see LVDS exporters in everything from smart home hubs to CNC machines. The reliability is well-proven. The MTBF for a typical exporter chip is over 1 million hours at 25°C. That's about 114 years. In practice, the connector and cable are the weak points. The 0.5 mm pitch FFC connectors have a rated life of 20,000 cycles, but in a high-vibration environment, they can fail sooner. That's why industrial designs often use locking connectors or screw terminals. The cable itself should be rated for the temperature and flexing requirements. For a robotic arm that moves constantly, you need a cable with a high flex life, like 10 million cycles. The LVDS exporter doesn't care about the cable type, as long as the impedance is matched. So the system designer has a lot of flexibility.
One more point: the LVDS exporter is not just for RGB data. Some systems use it for camera interfaces or data links. The same chip can serialize any parallel data stream, not just video. But in practice, 99% of applications are for displays. The timing and control signals are optimized for video, so using it for other data types requires careful design. The data enable signal acts as a frame sync, and the HSYNC and VSYNC are used for line and frame boundaries. If you're sending non-video data, you need to generate these signals artificially.